1. Field of the Invention
The present invention relates to a semiconductor integrated circuit and, more particularly, to a semiconductor integrated circuit including an input/output circuit for receiving and processing signals having different levels.
2. Description of the Related Art
FIG. 1 shows a conventional input circuit for use in an LSI operated at a CMOS level (0 to 5 V), and designed to receive an external ECL level (-0.8 to -1.7 V) signal.
More specifically, when the ECL level of an input terminal 1 is high, a differential bipolar transistor 2 is turned on, and a current is not supplied to a resistor 3. Therefore, the potential of the emitter of a bipolar transistor 4 goes to high level, and a high signal set at the CMOS level appears at an output terminal 5.
On the other hand, when the ECL level of the input terminal 1 is low, a differential bipolar transistor 6 is turned on, and a current is supplied to the resistor 3. Therefore, the emitter potential of the bipolar transistor 4 goes to low level, and a low signal set at the CMOS level appears at the output terminal 5. Note that a voltage of 5 V is applied to a terminal 7, and a voltage of -5.2 V is applied to a terminal 8.
FIG. 2 shows a conventional output circuit for outputting an ECL level signal from an LSI operated at the CMOS level.
More specifically, the CMOS level signal at a terminal 11 is lowered through the base--emitter paths (0.7 V.times.3) of bipolar transistors 12, 13, and 14, and an ECL level signal can be obtained at an output terminal 15. Note that a voltage of 5 V is applied to a terminal 16. The output circuit shown in FIG. 2 is disclosed in "Fabrication and Evaluation of the ECL/TTL Compatible BI-CMOS Gate Array", T. IEE Japan, Vol. 108-C, No. 12, 1988, Y. Sugimoto, H. Hara et al.
In the above-mentioned input circuit shown in FIG. 1, an ECL negative power source (-5.2 V) must be arranged inside the LSI operated at the CMOS level. In addition, a maximum voltage of about 10 V is applied to the collector--emitter path of the differential bipolar transistor 6. The withstand voltage of the circuit may be a bar to the development of a high-speed and micropatterned device.
In addition, in the output circuit shown in FIG. 2, temperature compensation is not performed. Therefore, the ECL level signal output from the output terminal is changed in accordance with changes in temperature. This poses a problem when an interface with a temperature-compensated circuit such as an ECL 100K series is used.